Requirement Details
Electron Ion Collider
G-DET-ELEC.1
Requirement details, history, relationships and interfaces associated with requirement G-DET-ELEC.1
CURRENT RECORD- ARCHIVE RECORDS
- RELATIONSHIPS
- INTERFACES
| Record Date: 07/14/2023 00:00 | |||
| Identifier: | G-DET-ELEC.1 | WBS: | 6.10.08 |
| Date Modified: | 07/14/2023 00:00 | TBD: | FALSE |
| Status Date: | 07/14/2023 00:00 | Status: | APPROVED |
| Description: | The EIC detector readout electronics shall provide the means to acquire, process and deliver detector signals to the DAQ system. Streaming readout shall be the default or nominal operation mode; to facilitate calibration and testing or debugging, a triggered operation mode shall be implemented at every level. | ||
| Comments: | |||
No archive versions
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| F-DET-ELEC.1 | The EIC detector readout electronics will provide signal conditioning to detector signals by the shaping constants, amplification, digitization and signal drive via discrete components and Application Specific Integrated Circuits (ASIC). |
| F-DET-ELEC.2 | The EIC detector readout electronics will process detector signals on the Front End Board (FEB). The FEB is typically characterized by the use of ASICs and customized for each type of sub-detector. Data transport off the FEB is made via optical fibers to FEPs or DAQ system. |
| F-DET-ELEC.3 | The EIC detector readout electronics will process, collect and aggregate data within the Front End Processor (FEP). The FEP is typically characterized by the use of FPGAs. Data transport off the FEP is made via optical fibers to the DAQ, which may consist of FELIX-type cards, network servers or network switches. |
| F-DET-ELEC.4 | The FEB and FEP boards will be remotely configured for proper operation of their programmable logic device, such as FPGAs. Processor boards or single board computers used with critical detector systems may require remote booting of OS. |
None defined.