Requirement Details
Electron Ion Collider
F-DET-ELEC.3
Requirement details, history, relationships and interfaces associated with requirement F-DET-ELEC.3
CURRENT RECORD- ARCHIVE RECORDS
- RELATIONSHIPS
- INTERFACES
| Record Date: 07/14/2023 00:00 | |||
| Identifier: | F-DET-ELEC.3 | WBS: | 6.10.08 |
| Date Modified: | 07/14/2023 00:00 | TBD: | FALSE |
| Status Date: | 07/14/2023 00:00 | Status: | APPROVED |
| Description: | The EIC detector readout electronics will process, collect and aggregate data within the Front End Processor (FEP). The FEP is typically characterized by the use of FPGAs. Data transport off the FEP is made via optical fibers to the DAQ, which may consist of FELIX-type cards, network servers or network switches. | ||
| Comments: | |||
No archive versions
| Parents | |
| G-DET-ELEC.1 | The EIC detector readout electronics shall provide the means to acquire, process and deliver detector signals to the DAQ system. Streaming readout shall be the default or nominal operation mode; to facilitate calibration and testing or debugging, a triggered operation mode shall be implemented at every level. |
| Children | |
| P-DET-ELEC.3 | FEP shall include FPGAs and interface via optical fibers to the FEPs and DAQ. Data aggregation (10:1), reduction techniques and processing via ML/AI algorithms shall reduce data volume by a factor of 10 or more during normal operation. |
None defined.